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this is information on a product in full production. june 2013 docid018946 rev 3 1/24 STGIPL20K60 sllimm? (small low-loss intelligent molded module) ipm, 3-phase inverter - 20 a, 600 v short-circuit rugged igbt datasheet - production data features ? ipm 20 a, 600 v 3-phase igbt inverter bridge including control ics for gate driving and free- wheeling diodes ? short-circuit rugged igbts ? v ce(sat) negative temperature coefficient ? 3.3 v, 5 v, 15 v cmos/ttl inputs comparators with hysteresis and pull down/pull up resistors ? undervoltage lockout ? internal bootstrap diode ? interlocking function ? smart shutdown function ? comparators for fault protection against overtemperature and overcurrent ? op amps for advanced current sensing ? dbc substrate leading to low thermal resistance ? isolation rating of 2500 v rms /min ? 5 k ntc for temperature control ? ul recognized: ul1557 file e81734 applications ? 3-phase inverters for motor drives ? home appliances, such as washing machines, refrigerators, air conditioners and sewing machines description this intelligent power module provides a compact, high performance ac motor drive in a simple, rugged design. combining st proprietary control ics with the most advanced short-circuit- rugged igbt system technology, this device is ideal for 3-phase inverters in applications such as home appliances and air conditioners. sllimm? is a trademark of stmicroelectronics. am01193v1 sdip-38l table 1. device summary order code marking package packaging STGIPL20K60 gipl20k60 sdip-38l tube www.st.com
contents STGIPL20K60 2/24 docid018946 rev 3 contents 1 internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3 2 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.1 ntc thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
docid018946 rev 3 3/24 STGIPL20K60 internal schematic diagram and pin configuration 24 1 internal schematic diagram and pin configuration figure 1. internal schematic diagram
internal schematic diagram and pin configuration STGIPL20K60 4/24 docid018946 rev 3 table 2. pin description pin symbol description 1out u high side reference output for u phase 2v boot u bootstrap voltage for u phase 3lin u low side logic input for u phase 4hin u high side logic input for u phase 5op- u op amp inverting input for u phase 6op out u op amp output for u phase 7op+ u op amp non inverting input for u phase 8cin u comparator input for u phase 9out v high side reference output for v phase 10 v boot v bootstrap voltage for v phase 11 lin v low side logic input for v phase 12 hin v high side logic input for v phase 13 op- v op amp inverting input for v phase 14 op out v op amp output for v phase 15 op+ v op amp non inverting input for v phase 16 cin v comparator input for v phase 17 out w high side reference output for w phase 18 v boot w bootstrap voltage for w phase 19 lin w low side logic input for w phase 20 hin w high side logic input for w phase 21 op- w op amp inverting input for w phase 22 op out w op amp output for w phase 23 op+ w op amp non inverting input for w phase 24 cin w comparator input for w phase 25 v cc low voltage power supply 26 sd / od shutdown logic input (active low) / open drain (comparator output) 27 gnd ground 28 t 2 ntc thermistor terminal 2 29 t 1 ntc thermistor terminal 1 30 n w negative dc input for w phase 31 w w phase output 32 p positive dc input 33 n v negative dc input for v phase 34 v v phase output
docid018946 rev 3 5/24 STGIPL20K60 internal schematic diagram and pin configuration 24 figure 2. pin layout (bottom view) 35 p positive dc input 36 n u negative dc input for u phase 37 u u phase output 38 p positive dc input table 2. pin description (continued) pin symbol description marking area
electrical ratings STGIPL20K60 6/24 docid018946 rev 3 2 electrical ratings 2.1 absolute maximum ratings table 3. inverter part symbol parameter value unit v pn supply voltage applied between p-n u , n v , n w 450 v v pn(surge) supply voltage (surge) applied between p-n u , n v , n w 500 v v ces each igbt collector emitter voltage (v in (1) = 0) 1. applied between hin i , lin i and gnd for i = u, v, w 600 v i c (2) 2. calculated according to the iterative formula: each igbt continuous collector current at t c = 25 c 20 a i cp (3) 3. pulse width limited by max junction temperature each igbt pulsed collector current 40 a p tot each igbt total dissipation at t c = 25 c 56 w t scw short circuit withstand time, v ce = 0.5 v (br)ces t j = 125 c, v cc = v boot = 15 v, v in (1) = 0 - 5 v 5 s table 4. control part symbol parameter min. max. unit v out output voltage applied between out u , out v , out w - gnd v boot - 21 v boot + 0.3 v v cc low voltage power supply - 0.3 21 v v cin comparator input voltage - 0.3 v cc + 0.3 v v op+ opamp non-inverting input - 0.3 v cc + 0.3 v v op- opamp inverting input - 0.3 v cc + 0.3 v v boot bootstrap voltage - 0.3 620 v v in logic input voltage applied between hin, lin and gnd - 0.3 15 v v sd /od open drain voltage - 0.3 15 v dv out /dt allowed output slew rate 50 v/ns i c t c () t jmax () t c ? r thj c ? v ce sat () max () t jmax () i c t c () , () ------------------------------------------------------------------------------------------------------- =
docid018946 rev 3 7/24 STGIPL20K60 electrical ratings 24 2.2 thermal data table 5. total system symbol parameter value unit v iso isolation withstand voltage applied between each pin and heatsink plate (ac voltage, t = 60 sec.) 2500 v t j power chips operating junction temperature -40 to 150 c t c module case operation temperature -40 to 125 c table 6. thermal data symbol parameter value unit r thjc thermal resistance junction-case single igbt 2.2 c/w thermal resistance junction-case single diode 4.5 c/w
electrical characteristics STGIPL20K60 8/24 docid018946 rev 3 3 electrical characteristics t j = 25 c unless otherwise specified. note: t on and t off include the propagation delay time of the internal drive. t c(on) and t c(off) are the switching time of igbt itself under the internally given gate driving condition. table 7. inverter part symbol parameter test condition value unit min. typ. max. v ce(sat) collector-emitter saturation voltage v cc = v boot = 15 v, v in (1) = 0 - 5 v, i c = 12 a -2.22.75 v v cc = v boot = 15 v, v in (1) = 0 - 5 v, i c = 12 a, t j = 125 c -1.8 i ces collector-cut off current (v in (1) = 0 ?logic state?) v ce = 550 v v cc = v boot = 15 v - 150 a v f diode forward voltage v in (1) = 0 ?logic state?, i c = 12 a - 1.7 2.1 v inductive load switching time and energy t on turn-on time v dd = 300 v, v cc = v boot = 15 v, v in (1) = 0 - 5 v, i c = 12 a (see figure 3 ) -915 ns t c(on) crossover time (on) - 155 t off turn-off time - 375 t c(off) crossover time (off) - 120 t rr reverse recovery time - 75 e on turn-on switching losses - 300 j e off turn-off switching losses - 170 1. applied between hini lin i and gnd for i = u, v, w (lin inputs are active-low).
docid018946 rev 3 9/24 STGIPL20K60 electrical characteristics 24 figure 3. switching time test circuit figure 4 "switching time definition" refers to hin inputs (active high). for lin inputs (active low), v in polarity must be inverted for turn-on and turn-off. figure 4. switching time definition v ce i c i c v in t on t c(on) v in(on) 10% i c 90% i c 10% v ce (a) turn-on (b) turn-off t rr 100% i c 100% i c v in v ce t off t c(off) v in(off) 10% v ce 10% i c am09223v1
electrical characteristics STGIPL20K60 10/24 docid018946 rev 3 3.1 control part table 8. low voltage power supply (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v cc_hys v cc uv hysteresis 1.2 1.5 1.8 v v cc_thon v cc uv turn on threshold 11.5 12 12.5 v v cc_thoff v cc uv turn off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 10 v sd/od = 5 v; lin = 5 v; h in = 0, c in = 0 450 a i qcc quiescent current v cc = 15 v sd/od = 5 v; lin = 5 v h in = 0, c in = 0 3.5 ma v ref internal comparator (cin) reference voltage 0.5 0.54 0.58 v table 9. bootstrapped voltage (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v bs_hys v bs uv hysteresis 1.2 1.5 1.8 v v bs_thon v bs uv turn on threshold 11.1 11.5 12.1 v v bs_thoff v bs uv turn off threshold 9.8 10 10.6 v i qbsu undervoltage v bs quiescent current v bs < 9 v sd/od = 5 v; lin and hin = 5 v; c in = 0 70 110 a i qbs v bs quiescent current v bs = 15 v sd/od = 5 v; lin and hin = 5 v; c in = 0 200 300 a r ds(on) bootstrap driver on resistance lvg on 120 w table 10. logic inputs (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit v il low logic level voltage 0.8 1.1 v v ih high logic level voltage 1.9 2.25 v i hinh hin logic ?1? input bias current hin = 15 v 110 175 260 a i hinl hin logic ?0? input bias current hin = 0 v 1 a i linl lin logic ?1? input bias current lin = 0 v 3 6 20 a i linh lin logic ?0? input bias current lin = 15 v 1 a i sdh sd logic ?0? input bias current sd = 15 v 30 120 300 a i sdl sd logic ?1? input bias current sd = 0 v 3 a dt dead time see figure 9 600 ns
docid018946 rev 3 11/24 STGIPL20K60 electrical characteristics 24 table 11. op amp characteristics (v cc = 15 v unless otherwise specified) symbol parameter test condition min. typ. max. unit v io input offset voltage v ic = 0 v, v o = 7.5 v 6 mv i io input offset current v ic = 0 v, v o = 7.5 v 440na i ib input bias current (1) 100 200 na v icm input common mode voltage range 0v v ol low level output voltage r l = 10 k to v cc 75 150 mv v oh high level output voltage r l = 10 k to gnd 14 14.7 v i o output short circuit current source , v id = +1; v o = 0 v 16 30 ma sink, v id = -1; v o = v cc 50 80 ma sr slew rate v i = 1 - 4 v; c l = 100 pf; unity gain 2.5 3.8 v/ s gbwp gain bandwidth product v o = 7.5 v 8 12 mhz a vd large signal voltage gain r l = 2 k 70 85 db svr supply voltage rejection ratio vs. v cc 60 75 db cmrr common mode rejection ratio 55 70 db 1. the direction of input current is out of the ic. table 12. sense comparator characteristics (v cc = 15 v unless otherwise specified) symbol parameter test conditions min. typ. max. unit i ib input bias current v cin = 1 v - 3 a v ol open-drain low-level output voltage i od = 3 ma - 0.5 v t d_comp comparator delay sd /od pulled to 5 v through 100 k resistor - 90 130 ns sr slew rate c l = 180 pf; r pu = 5 k -60 v/ sec t sd shutdown to high / low side driver propagation delay v out = 0, v boot = v cc , v in = 0 to 3.3 v 50 125 200 ns t isd comparator triggering to high / low side driver turn-off propagation delay measured applying a voltage step from 0 v to 3.3 v to pin cin i 50 200 250
electrical characteristics STGIPL20K60 12/24 docid018946 rev 3 note: x: don?t care. 3.1.1 ntc thermistor table 13. truth table condition logic input (v i ) output sd /od lin hin lvg hvg shutdown enable half-bridge 3-state lxxll interlocking half-bridge 3-state hlhll 0 ??logic state? half-bridge 3-state hhl l l 1 ?logic state? low side direct driving hllhl 1 ?logic state? high side direct driving hhhlh figure 5. maximum i c(rms) current vs. switching frequency (1) figure 6. maximum i c(rms) current vs. f sine (1) 1. simulated curves refer to typical igbt parameters and maximum r thj-c. am09907v1 0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 4 8 12 16 20 i c(rms) [a] f sw [khz] v pn = 300 v, modulaon index = 0.8, pf = 0.6, t j = 150 c, f sine = 60 hz t c = 80 c t c = 100 c am09908v1 8 9 10 11 12 13 14 15 16 17 18 1 10 100 i c(rms) [a] f sine [hz] fsw = 12 khz fsw = 20 khz fsw = 16 khz v pn = 300 v, modulaon index = 0.8, pf = 0.6, t j = 150 c, t c = 100 c table 14. ntc thermistor symbol parameter test conditions min. typ. max. unit. r 25 resistance t ntc = 25c to 85c 5 k r 125 resistance t ntc = 125c 300 b b-constant t c = 25c to 85c 3340 k t operating temperature -40 125 c
docid018946 rev 3 13/24 STGIPL20K60 electrical characteristics 24 equation 1: resistance variation vs. temperature where t are temperatures in kelvin rt () r 25 e b 1 t --- 1 298 --------- - ? ?? ?? ? = figure 7. ntc resistance vs. temperature figure 8. ntc resistance vs. temperature zoom 0 20 40 60 80 100 ntc (k ) -40 -20 0 20 40 60 80 100 t (c) am03795v2 0 0.2 0.4 0.6 0.8 1.0 ntc (k ) 50 60 70 80 90 100 110 120 t (c) 1.2 1.4 1.6 1.8 max min typ am03795_2v3
electrical characteristics STGIPL20K60 14/24 docid018946 rev 3 3.2 waveform definitions figure 9. dead time and interlocking waveforms definitions lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking control signal edges overlapped: interlocking + dead time control signals edges synchronous (*): dead time control signals edges not overlapped, but inside the dead time: dead time control signals edges not overlapped, outside the dead time: direct driving interlocking interlocking g gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state)
docid018946 rev 3 15/24 STGIPL20K60 smart shutdown function 24 4 smart shutdown function the STGIPL20K60 integrates a comparator for fault sensing purposes. the comparator non-inverting input (cin) can be connected to an external shunt resistor in order to implement a simple overcurrent protection function. when the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the half- bridge in 3-state. in the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a rc network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the outputs. the time delay between the fault and the outputs turn-off is no more dependent on the rc values of the external network connected to the shutdown pin. at the same time the internal logic turns on the open-drain output and holds it on until the shutdown voltage goes below the logic input lower threshold. finally the smart shutdown function provides the possibility to increase the real disable time without increasing the constant time of the external rc network.
smart shutdown function STGIPL20K60 16/24 docid018946 rev 3 figure 10. smart shutdown timing waveforms pls refer to table 12 for internal propagation delay time details. sd/od from/to controller v bias c sd r sd smart sd logic r on_od shut down circuit r pd_sd an approximation of the disable time is given by: where: hin/lin hvg/lvg open drain gate (internal) comp vref cp+ protection fast shut down : the driver outputs are set in sd state immediately after the comparator triggering even if the sd signal has not yet reach the lower input threshold disable time sd/od am12947v1
docid018946 rev 3 17/24 STGIPL20K60 application information 24 5 application information figure 11. typical application circuit
application information STGIPL20K60 18/24 docid018946 rev 3 5.1 recommendations ? input signal hin is active high logic. a 85 k (typ.) pull down resistor is built-in for each high side input. if an external rc filter is used, for noise immunity, pay attention to the variation of the input signal level. ? input signal lin is active low logic. a 720 k (typ.) pull-up resistor, connected to an internal 5 v regulator through a diode, is built-in for each low side input. ? to prevent the input signals oscillation, the wiring of each input should be as short as possible. ? by integrating an application specific type hvic inside the module, direct coupling to mcu terminals without any opto-coupler is possible. ? each capacitor should be located as nearby the pins of ipm as possible. ? low inductance shunt resistors should be used for phase leg current sensing. ? electrolytic bus capacitors should be mounted as close to the module bus terminals as possible. additional high frequency ceramic capacitor mounted close to the module pins will further improve performance. ? the sd /od signal should be pulled up to 5 v / 3.3 v with an external resistor (see section 4: smart shutdown function for detailed info). for further details refer to an3338. table 15. recommended operating conditions symbol parameter conditions value unit min. typ. max. v pn supply voltage applied between p-nu, nv, nw 300 400 v v cc control supply voltage applied between v cc -gnd 13.5 15 18 v v bs high side bias voltage applied between v booti -out i for i = u, v, w 13 18 v t dead blanking time to prevent arm-short for each input signal 1 s f pwm pwm input signal -40c < t c < 100c -40c < t j < 125c 20 khz t c case operation temperature 100 c
docid018946 rev 3 19/24 STGIPL20K60 package mechanical data 24 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. please refer to dedicated technical note tn0107 for mounting instructions. table 16. sdip-38l mechanical data dimensions mm. min. typ. max. a 49.10 49.60 50.10 a1 1.10 1.30 1.50 a2 1.40 1.60 1.80 a3 44.10 44.60 45.10 b 24.00 24.50 25.00 b1 11.25 11.85 12.45 b2 27.10 27.60 28.10 b3 28.60 29.10 29.60 c 5.00 5.40 6.00 c1 6.50 7.00 7.50 c2 10.35 10.85 11.35 e 1.10 1.30 1.50 e1 3.20 3.40 3.60 e2 5.80 6.00 6.20 e3 4.60 4.80 5.00 e4 5.60 5.80 6.00 e5 6.30 6.50 6.70 e6 4.50 4.70 4.90 d 38.10 d1 5.75 e11.80 e1 2.15 f 0.85 1.00 1.15 f1 0.35 0.50 0.65 r 1.55 1.75 1.95
package mechanical data STGIPL20K60 20/24 docid018946 rev 3 figure 12. sdip-38l package dimensions t 0.45 0.55 0.65 v0 6 table 16. sdip-38l mechanical data (continued) 8142868_g
docid018946 rev 3 21/24 STGIPL20K60 package mechanical data 24 figure 13. sdip-38l shipping tube type a (dimensions are in mm.) 8147106_e
package mechanical data STGIPL20K60 22/24 docid018946 rev 3 figure 14. sdip-38l shipping tube type b (dimensions are in mm.) 8147106_e
docid018946 rev 3 23/24 STGIPL20K60 revision history 24 7 revision history table 17. document revision history date revision changes 16-jun-2011 1 initial release 28-aug-2012 2 modified: min. and max. value table 4 on page 6 . updated: figure 13 on page 21 . added: figure 14 on page 22 . 17-jun-2013 3 updated figure 9: dead time and interlocking waveforms definitions .
STGIPL20K60 24/24 docid018946 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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